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AX88780
High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
Features
Document No: AX88780/V1.0/10/4/05
High-performance non-PCI local bus 16/32-bit SRAM-like host interface Support big/little endian data bus type Large embedded SRAM for packet buffers 32K bytes for receive buffer 8K bytes for transmit buffer Support IP/TCP/UDP checksum offloads Support interrupt with high or low active trigger mode Single-chip Fast Ethernet controller Compatible with IEEE802.3, 802.3u standards Integrated Fast Ethernet MAC/PHY transceiver in one chip Support 10Mbps and 100Mbps data rate Support full and half duplex operations Support 10/100Mbps N-way Auto-negotiation operation Support IEEE 802.3x flow control for full-duplex operation

Support back-pressure flow control for half-duplex operation Support packet length set by software Support optional MII interface for Ethernet PHY and HomePNA/HomePlug PHY applications Support Wake-on-LAN function by following events Detection of a change in the network link state Receipt of a Magic Packet Support optional EEPROM interface Support PCMCIA in 16-bit mode Support system reference clock from 40MHz to 100MHz Support LED pins for various network activity indications Integrated voltage regulator and 25MHz crystal oscillator 3.3V power supply with 5V I/O tolerance 128-pin LQFP with CMOS process, RoHS package US patent approved
Product Description
The AX88780 is a high-performance and cost-effective single-chip Fast Ethernet controller for various embedded systems including consumer electronics and home network markets that require a higher level of network connectivity. The AX88780 supports 16/32-bit SRAM-like host interface and integrates on-chip Fast Ethernet MAC and PHY, which is IEEE802.3 10Base-T and IEEE802.3u 100Base-T compatible. The AX88780 supports full-duplex or half-duplex operation at 10/100Mbps speed with auto-negotiation or manual setting. The AX88780 integrates large embedded SRAM for packet buffers to accommodate high bandwidth applications and supports IP/TCP/UDP checksum to offload processing loading from microprocessor/microcontroller in an embedded system.
System Block Diagram
Always contact ASIX for possible updates before starting a design. This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558
Released Date: 10/4/2005 http://www.asix.com.tw/
AX88780
Target Applications
Multimedia applications Content distribution application Audio distribution system (Whole-house audio) Video-over IP solutions, IP PBX and video phone Video distribution system, multi-room PVR Cable, satellite, and IP set-top box Digital video recorder DVD recorder/player High definition TV Digital media client/server Home gateway IPTV for triple play Others Printer, kiosk, security system Wireless router & access point
Applications
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Content
AX88780
1.0 Introduction.......................................................................................................................................................................6 1.1 General Description .......................................................................................................................................................6 1.2 AX88780 Block Diagram...............................................................................................................................................6 1.3 AX88780 Pinout Diagram..............................................................................................................................................7 2.0 Signal Description .............................................................................................................................................................8 2.1 Signal Type Definition ...................................................................................................................................................8 2.2 Host Interface.................................................................................................................................................................8 2.3 EEPROM Interface (Optional).......................................................................................................................................9 2.4 Regulator Interface.......................................................................................................................................................10 2.5 10/100M PHY Interface ...............................................................................................................................................10 2.6 MII Interface (optional)................................................................................................................................................10 2.7 Miscellaneous ..............................................................................................................................................................11 2.8 Power/ground pin.........................................................................................................................................................11 3.0 Functional Description ...................................................................................................................................................12 3.1 Host Interface...............................................................................................................................................................12 3.2 System Address Range.................................................................................................................................................12 3.3 TX Buffer Operation ....................................................................................................................................................12 3.4 RX Buffer Operation....................................................................................................................................................12 3.5 Flow Control ................................................................................................................................................................13 3.6 Checksum Offloads and Wake-up ................................................................................................................................13 3.7 Fast-Mode support .......................................................................................................................................................13 3.8 Big/Little-endian support .............................................................................................................................................13 3.9 10/100BASE-TX PHY.................................................................................................................................................13 3.10 16-bit Mode................................................................................................................................................................14 3.11 EEPROM Format .......................................................................................................................................................14 4.0 Register Description........................................................................................................................................................16 4.1 CMD--Command Register ...........................................................................................................................................17 4.2 IMR--Interrupt Mask Register .....................................................................................................................................17 4.3 ISR--Interrupt Status Register......................................................................................................................................18 4.4 TX_CFG--TX Configuration Register .........................................................................................................................19 4.5 TX_CMD--TX Command Register .............................................................................................................................19 4.6 TXBS--TX Buffer Status Register ...............................................................................................................................19 4.7 PHY_CTRL-- Internal PHY Control Register .............................................................................................................20 4.8 TXDES0--TX Descriptor0 Register.............................................................................................................................21 4.9 TXDES1--TX Descriptor1 Register.............................................................................................................................21 4.10 TXDES2--TX Descriptor2 Register...........................................................................................................................21 4.11 TXDES3--TX Descriptor3 Register ...........................................................................................................................22 4.12 RX_CFG--RX Configuration Register.......................................................................................................................22 4.13 RXCURT--RX Current Pointer Register ....................................................................................................................22 4.14 RXBOUND--RX Boundary Pointer Register ............................................................................................................23 4.15 MAC_CFG0--MAC Configuration0 Register............................................................................................................23 4.16 MAC_CFG1--MAC Configuration1 Register............................................................................................................23 4.17 MAC_CFG2--MAC Configuration2 Register............................................................................................................24 4.18 MAC_CFG3--MAC Configuration3 Register............................................................................................................24 4.19 TXPAUT--TX Pause Time Register ...........................................................................................................................24 4.20 RXBTHD0--RX buffer Threshold0 Register .............................................................................................................25 4.21 RXBTHD1--RX Buffer Threshold1 Register ............................................................................................................25 4.22 RXFULTHD--RX Buffer Full Threshold Register.....................................................................................................25 4.23 MISC--Misc. Control Register .................................................................................................................................25 4.24 MACID0--MAC ID0 Register ...................................................................................................................................26 4.25 MACID1--MAC ID1 Register ...................................................................................................................................26 4.26 MACID2--MAC ID2 Register ...................................................................................................................................26 4.27 TXLEN--TX Length Register ....................................................................................................................................26
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4.28 RXFILTER--RX Packet Filter Register .....................................................................................................................27 4.29 MDIOCTRL--MDIO Control Register ......................................................................................................................27 4.30 MDIODP--MDIO Data Port Register ........................................................................................................................28 4.31 GPIO_CTRL--GPIO Control Register.......................................................................................................................28 4.32 RXINDICATOR--Receive Indicator Register............................................................................................................28 4.33 TXST--TX Status Register .........................................................................................................................................29 4.34 MDCLKPAT--MDC Clock Pattern Register ..............................................................................................................29 4.35 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter...............................................................................29 4.36 RXCRCNT--RX CRC Error Counter.........................................................................................................................29 4.37 TXFAILCNT--TX Fail Counter .................................................................................................................................30 4.38 PROMDPR--EEPROM Data Port Register ...............................................................................................................30 4.39 PROMCTRL--EEPROM Control Register ................................................................................................................30 4.40 MAXRXLEN--Max. RX Packet Length Register......................................................................................................30 4.41 HASHTAB0--Hash Table0 Register ..........................................................................................................................31 4.42 HASHTAB1--Hash Table1 Register ..........................................................................................................................31 4.43 HASHTAB2--Hash Table2 Register ..........................................................................................................................31 4.44 HASHTAB3--Hash Table3 Register ..........................................................................................................................31 4.45 DOGTHD0--Watch Dog Timer Threshold0 Register ...............................................................................................31 4.46 DOGTHD1--Watch Dog timer Threshold1 Register ................................................................................................32 5.0 PHY Register...................................................................................................................................................................33 5.1 BMCR--Basic Mode Control Register.........................................................................................................................33 5.2 BMSR--Basic Mode Status Register............................................................................................................................34 5.3 PHYIDR0--PHY Identifier 0 Register .........................................................................................................................34 5.4 PHYIDR1--PHY Identifier 1 Register .........................................................................................................................35 5.5 ANAR--Auto-negotiation Advertisement Register ......................................................................................................35 5.6 ANLPAR--Auto-negotiation Link Partner Ability Register .........................................................................................35 5.7 ANER--Auto-negotiation Expansion Register .............................................................................................................36 6.0 Electrical Specification and Timings ..........................................................................................................................37 6.1 DC Characteristics .......................................................................................................................................................37 6.1.1 Absolute Maximum Ratings..................................................................................................................................37 6.1.2 General Operation Conditions .............................................................................................................................37 6.1.3 Leakage Current and Capacitance.......................................................................................................................37 6.1.4 DC Characteristics of 2.5V IO Pins .....................................................................................................................37 6.1.5 DC Characteristics of 3.3V IO Pins .....................................................................................................................38 6.1.6 Transmission Characteristics ...............................................................................................................................38 6.1.7 Reception Characteristics ....................................................................................................................................38 6.1.8 Power Consumption .............................................................................................................................................39 6.1.9 Thermal Characteristics.......................................................................................................................................39 6.2 A.C. Timing Characteristics .........................................................................................................................................40 6.2.1 Host Clock ............................................................................................................................................................40 6.2.2 Reset Timing .........................................................................................................................................................40 6.2.3 Host Single Write Timing...................................................................................................................................40 6.2.4 Host Fast Write Timing.........................................................................................................................................41 6.2.5 Host Single Read Timing ......................................................................................................................................41 6.2.6 Host Fast Read Timing .........................................................................................................................................41 6.2.7 MII Receive Timing (100Mb/s) .............................................................................................................................42 6.2.8 MII Transmit Timing (100Mbps) ..........................................................................................................................42 6.2.9 MDIO Timing .......................................................................................................................................................43 6.2.10 Serial EEPROM Timing .....................................................................................................................................44 7.0 Package Information ......................................................................................................................................................45 Ordering Information...........................................................................................................................................................46 Appendix................................................................................................................................................................................47 Revision History....................................................................................................................................................................48
AX88780
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AX88780
List of Figures
Figure 1 : AX88780 block diagram .......................................................................................................................................6 Figure 2 : AX88780 pin connection diagram.........................................................................................................................7 Figure 3 : 32-bit mode address mapping..............................................................................................................................12 Figure 4 : data swap block ...................................................................................................................................................13 Figure 5 : 16-bit mode map block........................................................................................................................................14 Figure 6 : Transmit waveform specification ........................................................................................................................38
List of Tables
Table 1 : Host Interface signals group ...................................................................................................................................8 Table 2 : EEPROM Interface signals group...........................................................................................................................9 Table 3 : Regulator signals group ........................................................................................................................................10 Table 4 : 10/100M Twisted-pair signals group.....................................................................................................................10 Table 5 : MII Interface signals group...................................................................................................................................10 Table 6 : Miscellaneous signals group ................................................................................................................................. 11 Table 7 : Power/Ground pins group ..................................................................................................................................... 11 Table 8 : MAC Register Mapping........................................................................................................................................16 Table 9 : PHY Register Mapping .........................................................................................................................................33
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AX88780
1.0 Introduction
1.1 General Description
AX88780 supports full-duplex or half-duplex operation at 10/100 Mbps speed with auto-negotiation or manual setting. The AX88780 has two built-in synchronous SRAMs for buffering packet. The one is 32K bytes for receiving packets from Ethernet; the other is 8K-bytes for transmitting packets from host system to Ethernet. The AX88780 also has 256 bytes built-in configuration registers. For software programming, the total address space used in AX88780 is 64K bytes in 32-bit mode and 16K bytes in 16-bit mode. Because AX88780 is a SRAM-like device, AX88780 could be treated as a SRAM device and be attached to SRAM controller of system. Therefore, system can execute DMA cycles to gain the highest performance. AX88780 needs 2 clock sources. One is the same to host system clock, and the operating frequency is from 40 MHz to 100 MHz. The other is 25Mhz for internal PHY running in MII mode.
1.2 AX88780 Block Diagram
Figure 1 : AX88780 block diagram
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AX88780
1.3 AX88780 Pinout Diagram
The AX88780 is housed in the 128-pin LQFP package.
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
VCC25A GNDA TXOP TXON GNDA XTLP XTLN VCC25A IBREF_WESD GNDA GNDA VCC25A RXIP RXIN GNDA VCC25A COL CRS VCC25 RXD3 RXD2 RXD1 RXD0 GND VCC25 RXCLK RXDV TXCLK NC NC TXEN TXD0
VCC33 HD14 HD13 VCC25 HD12 HD11 HD10 GND HD9 HD8 HD7 HD6 VCC33 HD5 HD4 HD3 HD2 HD1 HD0 VCC25 HA15 HA14 HA13 HA12 HA11 HA10 VCC25 HA9 HA8 HA7 HA6 HA5
RSTPB VCC25A GNDA VCC25A GNDA INTN RST_N HCLK VCC33 GND VCC25 HD31 HD30 HD29 HD28 HD27 HD26 HD25 WAKEUP HD24 VCC25 HD23 VCC33 HD22 HD21 HD20 VCC25 HD19 HD18 HD17 HD16 HD15
AX88780
Non-PCI 16/32-bit 10/100M Fast Ethernet Controller with Embedded PHY
VCC25 TXD1 TXD2 TXD3 VCC25 MDIO MDC VCC25 GND LINKLED SPDLED TEST1 TEST0 NA EEDO EEDI EECS EECLK PHYINTN CSN WEN OEN HA1 HA2 VCC33 REG_EN V25OUT VCC33R GNDR VCC25 HA3 HA4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AX88780
Figure 2 : AX88780 pin connection diagram
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AX88780
2.0 Signal Description
2.1 Signal Type Definition
I3: I2: O3: O2: IO3: TSO: OD: PD: PU: GND: GNDA: GNDR: VCC3: VCC3R: VCC2: VCC2A: I: O: IO: Input, 3.3V with 5V tolerance Input, 2.5V with 3.3V tolerance Output, 3.3V Output, 2.5V Input/Output, input 3.3V with 5V tolerance Tri-State Output Open Drain allows multiple devices to share as a wire-OR Internal 75K Pull Down Internal 75K Pull Up Digital Ground Analog Ground Ground for Regulator 3.3V power 3.3V for regulator 2.5V power 2.5V for analog Input only Output only Input/Output
2.2 Host Interface
Table 1 : Host Interface signals group
Pin Name INTN Type TSO, 8mA Pin NO 102 Pin Description Interrupt to host system When the polarity is active high, this signal must be pulled low, otherwise pulled high in active low environment. Software set the bit6 of command register (CMD) to response the polarity. Reset signal: active low. System Clock. The reference frequency is from 40MHz to 100MHz Wake-up signal to system. When the polarity is active high, this signal must be pulled low, otherwise pulled high in active low environment. Software set the bit0 of command register (CMD) to response the polarity. Data bus bit0. Data bus bit1. Data bus bit2. Data bus bit3. Data bus bit4. Data bus bit5. Data bus bit6. Data bus bit7. Data bus bit8. Data bus bit9. Data bus bit10. Data bus bit11. Data bus bit12. Data bus bit13. Data bus bit14. Data bus bit15. Data bus bit16, internal pull low.
RST_N HCLK WAKEUP HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16
I3 I3 TSO, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA
103 104 115 19 18 17 16 15 14 12 11 10 9 7 6 5 3 2 128 127
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AX88780
HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HA1 HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 WEN CSN OEN IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8m IO3, 8mA IO3, 8mA I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 126 125 124 122 121 120 118 116 114 113 112 111 110 109 108 42 41 34 33 32 31 30 29 28 26 25 24 23 22 21 44 45 43 Data bus bit17, internal pull low. Data bus bit18, internal pull low. Data bus bit19, internal pull low. Data bus bit20, internal pull low. Data bus bit21, internal pull low. Data bus bit22, internal pull low. Data bus bit23, internal pull low. Data bus bit24, internal pull low. Data bus bit25, internal pull low. Data bus bit26, internal pull low. Data bus bit27, internal pull low. Data bus bit28, internal pull low. Data bus bit29, internal pull low. Data bus bit30, internal pull low. Data bus bit31, internal pull low. Address bus bit1. Address bus bit2. Address bus bit3. Address bus bit4. Address bus bit5. Address bus bit6. Address bus bit7. Address bus bit8. Address bus bit9. Address bus bit10. Address bus bit11. Address bus bit12. Address bus bit13. Address bus bit14. Address bus bit15. Data Write Enable: WEN is driven by Host site, and it is active low. Chip Select Enable. CSN is driven by host site. It is active low. Data Output Enable: OEN is driven by the host site, and it is active low.
2.3 EEPROM Interface (Optional)
Table 2 : EEPROM Interface signals group
Pin Name EECLK EECS EEDI EEDO Type O3, 12mA O3, 12mA O3, 12mA I3, PD Pin No. 47 48 49 50 Pin Description A low speed clock to EEPROM Chip select to EEPROM device. This pin will be treated as full-duplex indicator when bit10 of PHY_CTRL register is set to high. It is active high in full-duplex mode, and low in half-duplex mode. Data to EEPROM, valid in EECS is high and EECLK in rising edge. This pin will be treated as collision indicator when bit10 of PHY_CTRL register is set to high. It is active high in collision indicator. Data from EEPROM
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AX88780
2.4 Regulator Interface
Table 3 : Regulator signals group
Pin Name VCC33R GNDR REG_EN V25OUT Type VCC3R GNDR I3 O2 Pin No. 37 36 39 38 Pin Description 3.3V power to internal regulator Ground pin for internal regulator High to enable internal regulator. Low to disable internal regulator. 2.5V output from internal regulator, max 250mA, when REG_EN pin is high.
2.5 10/100M PHY Interface
Table 4 : 10/100M Twisted-pair signals group
Pin Name RXIN RXIP TXON TXOP Type I I O O Pin No. 83 84 93 94 Pin Description Differential received input signal for both 10BASE-T and 100BSE-TX modes. Differential received input signal for both 10BASE-T and 100BSE-TX modes. Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes. Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes
2.6 MII Interface (optional)
Table 5 : MII Interface signals group
Pin Name TXEN TXD[3:0] TXCLK RXCLK RXD[3:0] RXDV COL CRS MDIO MDC Type O2, 12mA O2, 12mA I2 I2 I2 I2 I2 I2 IO3, 8mA,PU O3, 8mA Pin No. Pin Description 66 Transmit Enable: TXEN is transition synchronously with respect to the rising edge of TXCLK. TXEN indicates that the port is presenting nibbles on TXD [3:0] for transmission. 61,62, Transmit Data: 63,65 TXD[3:0] is transition synchronously with respect to the rising edge of TXCLK. 69 Transmit Clock: TXCLK is a continuous clock from PHY. It provides the timing reference for the transfer of the TXEN and TXD[3:0] signals from the MII port of PHY. 71 Receive Clock: RXCLK is a continuous clock that provides the timing reference for the transfer of the RXDV, RXD[3:0]. 74,75, Receive Data: 76,77 RXD[3:0] is driven by the PHY synchronously with respect to RXCLK. 70 Receive Data Valid: RXDV is driven by the PHY synchronously with respect to RXCLK. Asserted high when valid data is present on RXD [3:0]. 80 Collision signal: This signal is driven by PHY when collision is detected. 79 Carrier Sense: Asynchronous signal CRS is asserted by the PHY when either the transmit or receive medium is non-idle. 59 Station Management Data Input /Output: Serial data input/Output transfers from/to the PHY. The transfer protocol conforms to the IEEE 802.3u MII specification. 58 Station Management Data Clock: The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. 46 An interrupt signal from PHY, active low.
PHYINTN I2
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2.7 Miscellaneous
Table 6 : Miscellaneous signals group
Pin Name LINKLED Type IO, 12mA, PD Pin No. 55 Pin Description In power-on reset phase, this pin will be latched by AX88780 to determine that system operates in 32 or 16-bit mode. High state is 16-bit mode and low state is 32-bit mode. The default is in 32-bit mode. Upon finishing reset status, if bit11 of PHY_CTRL register is enabled, this pin stands for: Link: indicates a good link status, active low in 16-bit mode and active high in 32-bit mode. Traffic: indicates the traffic status and flashes while in TX or RX state. If bit11 of PHY_CTRL is not enabled, this pin is as general-purpose pin and controlled by GPIO_CTRL register. In power-on reset phase, this pin will be latched by AX88780 to determine whether AX88780 swaps the data or not. If the high state, AX88780 will sap the data. The default is little-endian. Upon finishing reset stage, if bit12 PHY_CTRL register is enabled, this pin stands for speed mode. Low indicates PHY is in 10BASE-TX mode, and high state indicates PHY in 100BASE-T mode. This pin is tied to ground for normal operation. Floating for normal operation. Floating for normal operation. 25MHz Crystal clock output. 25MHz Crystal clock input. (Note: 50ppm, max. 33pF load capacitance) Power-up reset signal. Active low. This pin must be connected with RST_N pin. Connect a 12.3Kohm resistor to ground. No connection
SPDLED
IO, 12mA, PD
54
NA TEST0 TEST1 XTLN XTLP RSTPB IBREF_WESD NC
I I3, PD I3, PD O3 I3 I3 I O3
51 52 53 90 91 97 88 67,68
2.8 Power/ground pin
Table 7 : Power/Ground pins group
Pin Name VCC33 VCC25 GND VCC25A GNDA Type VCC3 VCC2 GND VCC2A GNDA Pin No. 1,13,40, 105, 119 4,20,27,35,57,60,64,72,78,107,117,123 8, 56, 73,106 81,85,89,96,98,100 82,86,87,92,95,99,101 Pin Description Digital 3.3V power Digital 2.5V power Digital ground 2.5V power for PHY analog part Analog ground
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AX88780
3.0 Functional Description
3.1 Host Interface AX88780 supports a very simple SRAM-like interface. There are only 3 control signals to operate the read or write. For write operation, host activates CSN and WEN to low with address and data bus. AX88780 will decode and latched the data into internal buffer. For normal operation, the WEN needs at least 3 clocks duration for one 32/16-bit write operation. The CSN can always be driven, but WEN must at least be de-asserted 1 clock before next access. For read operation, host asserts CSN and OEN at least 3 clocks to AX88780, the data will be valid after 3 clocks. For asynchronous access, please add extra 3 clocks to read or write. 3.2 System Address Range AX88780 is suitable to attach to SRAM controller, so it needs 64K memory space to operate. The designer can allocate any block (64K) in system space. From offset 0000h to 7FFFh is for RX operation, and offset 8000h to F000h is for TX operation. The internal configuration register of AX88780 is allocated in offset FC00h to FCFFh. Below is the mapping of addressing.
31
0
X X X X _0000h
R X a re a 3 2 7 6 8 b y te s
X X X X _8000h
T X a re a 3 1 7 4 4 b y te s
R e g is te rs a re a 2 5 6 b y te s
N o u se d a re a 7 6 8 b y te s
X X X X _FC 00h
X X X X _FD 00h
X X X X _FFFFh
Figure 3 : 32-bit mode address mapping
3.3 TX Buffer Operation AX88780 employs 4 descriptors to maintain transmit information, such as packet length, start bit. These descriptors are located in offset FC20h, FC24h, FC28h and FC2Ch. Driver can choose any descriptor whenever there is data need to be transmitted. Since there are only 4 descriptors, upon running out of descriptors, driver must wait for the descriptor is to be released by AX88780. 3.4 RX Buffer Operation AX88780 is built a 32K SRAM for RX operation. It utilizes ring structure to maintain the input data from PHY and read out to host. There are two pointer registers located in offset FC34h and FC38h. AX88780 will maintain RXBOUND0 register. Upon it receives a valid packet from PHY it will update RXBOUND0 according to the packet length. Driver reads data from AX88780 and maintains the RXBOUND1 register. When driver finishes reading packet, it must update RXBOUND1 according to the packet length. AX88780 utilizes RXBOUND0 and RXBOUND1 to provide receive buffer status, full or empty.
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3.5 Flow Control In full duplex mode, AX88780 supports the standard flow control mechanism defined in IEEE 802.3x standard. It enables the stopping of remote node transmissions via a PAUSE frame information interaction. When space of the packet buffer is less than the threshold values (RXBTHD0, RXBTHD1), AX88780 will send out a PAUSE-ON packet to stop the remote node transmission. And then AX88780 will send out a PAUSE-OFF packet to inform the remote node to retransmit packet if it has enough space to receive packets. 3.6 Checksum Offloads and Wake-up To reduce the computing loading of CPU, AX88780 is built checksum operator for IP, UDP or TCP packet. AX88780 will detect the packet whether it is IP, UDP or TCP packet. If it is an IP packet, AX88780 will calculate the checksum of header and put the result in checksum filed of IP. Then it continuously checks the packet whether it is UDP or TCP. It will perform the checksum operation whenever it is a UDP or TCP packet. AX88780 also automatically skip the VLAN tag when checksum is executed. AX88780 also supports to detect magic packet or link-up to wake up system when system is in sleep state. 3.7 Fast-Mode support To improve the throughput in embedded system, AX88780 supports fast-mode for TX/RX buffer access. Host can access AX88780 by driving CSN to low and toggle WEN (write) or OEN (read). AX88780 can support the burst until whole packet access. The access timing can refer to section 6.2.4 and 6.2.6. This mechanism is only for TX/RX buffer access. For configuration register access, it must use single-burst. 3.8 Big/Little-endian support AX88780 supports "Big" or "Little" endian data format. The default is Little-endian. Designer can pull-up SPDLED pin to high to swap the data format. Below table can depict the relation. This swap is only valid in 32-bit mode.
AX88780
D [3 1 :2 4 ]
D [2 3 :1 6 ]
D [1 5 :8 ]
D [7 :0 ]
L ittle -e n d ia n
D [7 :0 ]
D [1 5 :0 ]
D [2 3 :1 6 ]
D [3 1 :2 4 ]
B ig -e n d ia n
Figure 4 : data swap block 3.9 10/100BASE-TX PHY AX88780 integrates high performance PHY that is fully compliant with 10/100BASE-TX Ethernet standards such as IEEE 802.3, IEEE 802.3u and ANSI X3.263-1995. It's main features can described below. Adaptive equalizer This equalizer mainly eliminates the distortions caused by inter-symbol interference (ISI) by automatically adjusting the mathematical coefficient to match the cable length. Baseline wander correct The transmitter sends DC and AC signals as a pair. The receiving device and transmitting device each have a transformer that blocks the Dc signal. When the AC signal loses its DC component, the AC signal becomes distorted. The Baseline-Wander correct ill restores the DC component to AC signal and delivers it as a complete signal to receiver. Link monitor/signal detect This feature is used to detect the signal's level. If the detected signal is above 400mV in 100BASE-TX mode, it will generate a Signal Detected (SD) to MAC. If the level is below 400mV, the SD signal will be de-asserted 1ms. Carrier detect and 4B/5B coding The Physical Coding Sub-layer (PCS) checks with Physical Medium Attachment (PMA) data to see if the packets meet IEEE 802.3u defined preamble (J/K/packets in 100BASE-TX) standards. If the packets meet the standards, the PCS sub-layer will start to process the data and send to MAC engine. The PCS converts received/transmitted data according IEEE 802.3u defined coding standards, such as 4B/5B and scrambling/de-scrambling.
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3.10 16-bit Mode AX88780 supports 16-bit mode operation. AX88780 will request a 16K bytes space for TX, RX and register access. The mapping mechanism can refer to below block. Firstly, the driver requests a 16K bytes space from system then sets the new mapped address to base + 6 to remap window base. Secondly, driver sets base address to `1' to start decoding.
AX88780
MEMBASE--Memory base Address
Field Name 15:1 0 DECODE_EN Type Default R/W All 0's R/W 0 Description Reserved. 16-bit decode enable Set to `1' to start decoding.
MEMBAS6--Memory base Address + 6
Field Name 15:8 7:0 WINSIZE Type Default Description R/W 8'h00 Reserved. R/W 8'h00 Window Base Pointer. (MSB only) This field defines another new windows base address for TX, RX and register access. The total size is 8K bytes. TX areas occupy 4K - 256 bytes Registers occupy 256 bytes. RX areas occupy 4K bytes.
Note: This address defines the window used in TX, RX and registers accessed in 16-bit mode. Refer to below mapping mechanism.
B a se a d d re ss
B a se a d d re ss + 6
15 0
XX
8 K b y te s
N e w b a se A d d re ss = 1 6 'h X X 0 0
T X a re a 3 8 4 0 b y te s
4 K b y te s
1 6 K b y te s
R e g is te r a re a 2 5 6 b y te s
R x a re a 4 0 9 6 b y te s
4 K b y te s
Figure 5 : 16-bit mode map block
Next example is to explain the address translation. If the starting address 24'h20_0000 is allocated to hardware then driver sets 16'h1000 to address 24'h20_0006. The new base address will be 24'h20_1000 now. The TX areas will be from 24'20_1000 to 24'h20_1EFF. The registers range will be from 24h20_1F00 to 24'h20_1FFF. The RX areas will be from 24'h20_2000 to 24'h20_2FFF. 3.11 EEPROM Format AX88780 will auto-load data from EEPROM device after hardware reset. If the EEPROM device is not attached, the loading operation will be discarded. The EEPROM mainly provides MAC address information and CIS information if it is used in PCMCIA environment. Below table is the format if EEPROM device is employed. Note: If the address of MAC is 48'h123456789ABC then the MACID0 will be 16'h9ABC, MACID1=16h'h5678 and MACID2=16'h1234.
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ASIX ELECTRONICS CORPORATION
Address 0 1 2 3 4 5 6 ~ 11 12 ~ 127 Pointer to CIS area start address MACID0 data MACID1 data MACID2 data Reserved, keep all 0's 1= PCMCIA, 0 = Non-PCMCIA 16-bit mode Reserved, keep all 0's CIS area, if it used in PCMCIA system
Description
AX88780
15
ASIX ELECTRONICS CORPORATION
AX88780
4.0 Register Description
There are some registers located from FC00h to FCFFh. All of the registers are 32-bit boundary alignment, but only low 16-bit are available (exception FC54h). For reserved bits, don't set them in normal operation. Table 8 : MAC Register Mapping Offset FC00h FC04h FC08h FC10h FC14h FC18h FC1Ch FC20h FC24h FC28h FC2Ch FC30h FC34h FC38h FC40h FC44h FC48h FC4Ch FC54h FC58h FC5Ch FC60h FC68h FC70h FC74h FC78h FC7Ch FC80h FC84h FC88h FC8Ch FC90h FC94h FCA0h FCA4h FCA8h FCACh FCB0h FCB4h FCB8h FCC0h FCC4h FCC8h FCCCh FCE0h FCE4h Name CMD IMR ISR TX_CFG TX_CMD TXBS PHY_CTRL TXDES0 TXDES1 TXDES2 TXDES3 RX_CFG RXCURT RXBOUND MAC_CFG0 MAC_CFG1 MAC_CFG2 MAC_CFG3 TXPAUT RXBTHD0 RXBTHD1 RXFULTHD MISC MACID0 MACID1 MACID2 TXLEN RXFILTER MDIOCTRL MDIODP GPIO_CTRL RXINDICATOR TXST MDCLKPAT RXCHKSUMCNT RXCRCNT TXFAILCNT PROMDPR PROMCTRL MAXRXLEN HASHTAB0 HASHTAB1 HASHTAB2 HASHTAB3 DOGTHD0 DOGTHD1 Description Command Register Interrupt Mask Register Interrupt Status Register TX Configuration Register TX Command Register TX Buffer Status Register Internal PHY Control Register TX Descriptor0 Register TX Descriptor1 Register TX Descriptor2 Register TX Descriptor3 Register RX Configuration Register RX Current Pointer Register RX Boundary Pointer Register MAC Configuration0 Register MAC Configuration1 Register MAC Configuration2 Register MAC Configuration3 Register TX Pause Time Register RX Buffer Threshold0 Register RX Buffer Threshold1 Register RX Buffer Full Threshold Register Misc. Control Register MAC ID0 Register MAC ID1 Register MAC ID2 Register TX Length Register RX Packet Filter Register MDIO Control Register MDIO Data Port Register GPIO Control Register Receive Indicator Register TX Status Register MDC Clock Pattern Register RX IP/UDP/TCP Checksum Error Counter RX CRC Error Counter TX Fail Counter EEPROM Data Port Register EEPROM Control Register MAX. RX packet Length Register Hash Table0 Register Hash Table1 Register Hash Table2 Register Hash Table3 Register Watch Dog Timer Threshold0 Register Watch Dog Timer Threshold1 Register Default value 32'h0000_0001 32'h0000_0000 32'h0000_0000 32'h0000_0040 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0100 32'h0000_0000 32'h0000_07FF 32'h0000_9157 32'h0000_6000 32'h0000_0100 32'h0000_060E 32'h001F_E000 32'h0000_0300 32'h0000_0600 32'h0000_0100 32'h0000_0003 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_05FC 32'h0000_002C 32'h0000_0000 32'h0000_0000 32'h0000_0003 32'h0000_0000 32'h0000_0000 32'h0000_8040 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0600 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_FFFF 32'h0000_0000
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ASIX ELECTRONICS CORPORATION
AX88780
4.1 CMD--Command Register
Offset Address = FC00h
Field Name 31:16 15 RXVLAN
Default = 32'h0000_0001
14
TXVLAN
13:10 9
RXEN
8
TXEN
7 6
INTMOD
5:1 0
WAKEMOD
Type Default Description R/W All 0's Reserved R/W 0 RX VLAN indicator Driver enables this bit to indicate AX88780 that the received packet will include 4 bytes VLAN tag, AX88780 will skip 4 bytes when it calculates the checksum of IP, TCP or UDP packet. 1 = enable 0 = disable R/W 0 TX VLAN indicator Driver enables this bit to indicate AX88780 that the transmitted packet will include 4 bytes VLAN tag, AX88780 will skip 4 bytes when it calculates the checksum of IP, TCP or UDP packet. 1 = enable 0 = disable R/W All 0's Reserved R/W 0 RX Function Enable When this bit is enabled, MAC starts to receive packets. 1 = enable 0 = disable R/W 0 TX Function Enable When this bit is enabled, MAC could start to transmit packet to Ethernet. 1 = enable 0 = disable R/W 0 Reserved R/W 0 Interrupt Active Mode Driver sets this bit to indicate AX88780 that the interrupt of system is activated high or low. 1: Active high 0: Active low R/W All 0's Reserved R/W 1 WAKEUP pin polarity Driver sets this bit to indicate AX88780 that the polarity of system wake-up signal is activated high or low. 1: Active high 0: Active low
4.2 IMR--Interrupt Mask Register
Offset Address = FC04h
Field Name 31:6 5 PHYMASK
Default = 32'h0000_0000
4
PRIM
Type Default Description R All 0's Reserved R/W 0 PHY interrupt Mask When this bit is enabled, an interrupt request from PHY set in bit 5 of Interrupt Status Register will make AX88780 to issue an interrupt to host. 1 = enable 0 = disable R/W 0 Packet Received Interrupt Mask When this bit is enabled, a received interrupt request set in bit 4 of Interrupt Status Register will make AX88780 to issue an interrupt to host. 1 = enable 0 = disable
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AX88780
3 PTIM R/W 0 Packet Transmitted Interrupt Mask When this bit is enabled, a transmitted interrupt request set in bit 3 of Interrupt Status Register will make AX88780 issue an interrupt to host. 1 = enable 0 = disable Reserved Watch Dog Timer Interrupt Mask When this bit is enabled, a watch dog timer expired interrupt request set in bit1 of Interrupt Status Register will make AX88780 to issue an interrupt to host 1 = enable 0 = disable Rx Buffer Full Interrupt Mask When this bit is enabled, a RX buffer full interrupt request set in bit 0 of Interrupt Status Register will make AX88780 to issue an interrupt to host. 1 = enable 0 = disable
2 1
DOGIM
R/W R/W
0 0
0
RXFULIM
R/W
0
4.3 ISR--Interrupt Status Register
Offset Address = FC08h
Field 31:6 5 Name PHYIG Type R R/W Default All 0's 0
Default = 32'h0000_0000
Description Reserved PHY Interrupt Generation If this bit is set to `1' it means there is an interrupt request from PHY. MAC will forward this interrupt to system. Meantime driver should poll PHY and adopt proper procedure. Write `1' to this bit to clear this request status. 1 = have interrupt request 0 = no interrupt request Receive Packet Interrupt Generation If this bit is set to `1' it means MAC receives a packet or (packets) from cable. The packet is kept in RX buffer. Write `1' to this bit to clear this request status. 1 = have received packet 0 = no received packet Finish Transmitting Packet Interrupt If this bit is set to `1' it means MAC had transmitted packet to cable. Write `1' to this bit to clear this request status. 1 = finish transmitting 0 = none Reserved Watch Dog Timer Expired Interrupt If this bit is set to `1' it means the WATCH DOG timer is expired. AX88780 will issue an interrupt to host. Write `1' to this bit to clear this request status. The expired duration can refer to DOGTHD0 and DOGTHD1 registers. 1 = timer expired happens 0 = none RX Buffer Full Interrupt If this bit is set to `1' it means RX buffer is full and no more packets will be received until packets are read out. Write `1' to this bit to clear this request status. 1 = RX buffer full 0 = None
4
RPIG
R/W
0
3
FTPI
R/W
0
2 1
WDTEI
R/W R/W
0 0
0
RXFULI
R/W
0
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ASIX ELECTRONICS CORPORATION
AX88780
4.4 TX_CFG--TX Configuration Register
Offset Address = FC10h
Field Name 31:7 6 TXCRCAP Type R R/W
Default = 32'h0000_0040
Default Description All 0's Reserved 1 TXCRC Auto-Append When this bit is enabled, AX88780 will append CRC to the transmitted packet in FCS field. 1 = enable 0 = disable 0 Reserved. 0 TX Checksum Generation When this bit is enabled, AX88780 will append checksum to the transmitted packet that is IP or TCP or UDP packet. 1 = enable 0 = disable 2'b00 Reserved 2'b00 TX Description Status AX88780 reports which descriptor is transmitted now Default: 2'b00
5 4
TXCHKSUM
R/W R/W
3:2 1:0
TXDS
R R
4.5 TX_CMD--TX Command Register
Offset Address = FC14h
Field 31:16 15 Name HWI Type R R/W Default All 0's 0
Default = 32'h0000_0000
Description Reserved Host Writes Indication Before host begins to send a packet to TX buffer, this bit should be set. At the end of host writes the packet, this bit should be cleared. 1 = Start Writing 0 = End Writing TX Descriptor Pointer To specify which TX descriptor to be written. Reserved Byte Count. Data length is written to transmitted buffer.
14:13 12 11:0
TXDP DATALEN
R/W R/W R/W
2'b00 0 All 0's
4.6 TXBS--TX Buffer Status Register
Offset Address = FC18h
Field Name 31:4 8 INTXDS Type R R Default All 0's 0
Default = 32'h0000_0000
Description Reserved Internal TX descriptor status. This bit reports the TX descriptor status. When there are data not to be transmitted, this bit will be set to `1' otherwise it will be `0' 1 = have data in TX buffer 0 = all data are transmitted to cable Reserved TX Descriptor In Transmitting These status bits indicate which descriptor is transmitting now. 00: Descriptor 0 in transmitting
7:6 5:4
TXDUSE
R R
2'b00 2'b00
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ASIX ELECTRONICS CORPORATION
3 2 1 0
TXD3O TXD2O TXD1O TXD0O
R/W R/W R/W R/W
0 0 0 0
01: Descriptor 1 in transmitting 10: Descriptor 2 in transmitting 11: Descriptor 3 in transmitting TX Descriptor3 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor3. transmission is finished, AX88780 will auto-clear this bit. TX Descriptor2 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor2. transmission is finished, AX88780 will auto-clear this bit. TX Descriptor1 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor1. transmission is finished, AX88780 will auto-clear this bit. TX Descriptor0 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor0. transmission is finished, AX88780 will auto-clear this bit.
AX88780
When the When the When the When the
4.7 PHY_CTRL-- Internal PHY Control Register
Offset Address = FC1Ch
Field 31:13 12 Name SPD_GPIO1 Type R R/W
Default = 32'h0000_0000
Default Description All 0's Reserved 0 Speed LED or GPIO1 When this bit is enabled, pin54 is as speed indicator, otherwise it is as GPIO1 function and controlled by GPIO_CTRL register. 1= enable 0= disable 0 Link LED or GPIO0 When this bit is enabled, pin55 is as link/traffic indicator, otherwise it is as GPIO0 function and controlled by GPIO_CTRL register. 1 = enable 0 = disable 0 EECS Pin as Full-Duplex LED When this bit is enabled, EECS pin will be as full-duplex indicator and EEDI pin will be as collision indicator. 1 = enable 0 = disable 0 Power down PHY When this bit is enabled, AX88780 will power down internal PHY. 1 = enable 0 = disable 0 PHY Selection When this bit is enabled, AX88780 will select internal PHY, otherwise it will select external PHY. 1 = enable 0 = disable 0 Reserved 3'b000 Internal 10/100M PHY operation mode Driver can set these bits to control internal PHY operation mode. 3'b000 = auto-negotiation enable with all capability 3'b001 = auto-negotiation with 100BASE-TX FDX/HDX ability 3'b010 = auto-negotiation with 10BASE-T FDX/HDX ability 3'b011 = Reserved 3'b100 = Manual selection of 100BASE-TX FDX 3'b101 = Manual selection of 100BASE-TX HDX 3'b110 = Manual selection of 10BASE-T FDX 3'b111 = Manual selection of 10BASE-T HDX
11
LNK_GPIO0
R/W
10
FUL_EECS
R/W
9
PWDN
R/W
8
PHY_EN
R/W
7 6:4
PHYOPMODE
R R/W
20
ASIX ELECTRONICS CORPORATION
3:1 0
-
R R/W
3'b000 0
Reserved Reserved, must to be 0
AX88780
4.8 TXDES0--TX Descriptor0 Register
Offset Address = FC20h
Field 31:16 15 Name TXD0_EN Type R R/W Default All 0's 0
Default = 32'h0000_0000
Description Reserved Transmit TX descriptor0 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, data had been written to TX descriptor0. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX packet length (unit: byte) Driver set this field to indicate AX88780 how many bytes will be transmitted.
14:13 12:0
TXD0_LEN
R R/W
2'b00 All 0's
4.9 TXDES1--TX Descriptor1 Register
Offset Address = FC24h
Field 31:16 15 Name TXD1_EN Type R R/W Default All 0's 0
Default = 32'h0000_0000
Description Reserved Transmit TX descriptor1 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, data had been written to TX descriptor1. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX packet length (unit: byte) Driver set this field to indicate AX88780 how many bytes will be transmitted.
14:13 12:0
TXD1_LEN
R R/W
2'b00 All 0's
4.10 TXDES2--TX Descriptor2 Register
Offset Address = FC28h
Field 31:16 15 Name TXD2_EN Type R R/W Default All 0's 0
Default = 32'h0000_0000
Description Reserved Transmit TX descriptor2 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, data had been written to TX descriptor2. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX packet length (unit: byte) Driver set this field to indicate AX88780 how many bytes will be
14:13 12:0
TXD2_LEN
R R/W
2'b00 All 0's
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ASIX ELECTRONICS CORPORATION
transmitted.
AX88780
4.11 TXDES3--TX Descriptor3 Register
Address = FC2Ch
Field 31:16 15 Name TXD3_EN Type R R/W
Default = 32'h0000_0000
Default All 0's 0 Description Reserved Transmit TX descriptor3 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, data had been written to TX descriptor3. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX Packet Length (unit: byte) Driver set this field to indicate AX88780 how many bytes will be transmitted.
14:13 12:0
TXD3_LEN
R R/W
2'b00 All 0's
4.12 RX_CFG--RX Configuration Register
Offset Address = FC30h
Field 31:9 8 Name RXFLOW Type R R/W
Default = 32'h0000_0100
Default All 0's 1 Description Reserved RX Flow Control To enable RX flow control, driver MUST set this bit and bit5 of MAC_CFG1. 1 = enable 0 = disable Reserved. RX Packet TCP/IP Checksum When this bit is set, AX88780 will check the checksum of the received packet that is IP, TCP or UDP packet. If there is checksum error, AX88780 will drop the packet and RXCHKSUMCNT counter will add 1. 1 = enable 0 = disable Reserved RX Buffer Protection When this bit is enabled, MAC will protect the RX buffer to avoid overrun. For normal operation, this bit should be enabled in initial stage. 1= enable 0= disable
7:5 4
RXCHKSUM
R/W R/W
3'b000 0
3:1 0
RXBUFPRO
R/W R/W
3'b000 0
4.13 RXCURT--RX Current Pointer Register
Offset Address = FC34h
Field 31:11 10:0 Name RXCURPTR Type R R/W Default All 0's All 0's
Default = 32'h0000_0000
Description Reserved RX Line Current Pointer. Point to the last line that will be written by hardware. The unit of line is 16 bytes. MAC will maintain this register.
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ASIX ELECTRONICS CORPORATION
AX88780
4.14 RXBOUND--RX Boundary Pointer Register
Offset Address = FC38h
Field 31:11 10:0 Name RXBUNPTR Type R R/W Default All 0's All 0's
Default = 32'h0000_07FF
Description Reserved RX Line Boundary Pointer. Point to the last line that has been read by driver. The unit of line is 16 bytes. When driver finished reading packet from RX buffer, it must update this field.
4.15 MAC_CFG0--MAC Configuration0 Register
Offset Address = FC40h
Field 31:16 15 Name SPEED100 Type R R/W Default All 0's 1
Default = 32'h0000_9157
Description Reserved Line Speed Mode When this bit is enabled, The MAC of AX88780 will operate in 100M speed, otherwise it will operate in 10M speed. The line speed must co-operate with setting of PHY. 1 = 100M 0 = 10M Reserved, this bit must set to 0 for normal operation Reserved, this bit must set to 0 for normal operation. TX Flow Control If this bit is enabled, MAC will perform TX flow control and send pause on/off frame when receive buffer become low water level. 1 = enable 0 = disable Reserved, this bit must set to 0 for normal operation. Inter Packet Gap time: (IPG) This field defines the back-to-back transmit packet gap for 10.100M only. Reserved, keep the default value for normal operation.
14 13 12
TXFLOW_EN
R/W R/W R/W
0 0 1
11 10:4 3:0
IPGT -
R/W R/W R/W
0 7'h15 4'h7
4.16 MAC_CFG1--MAC Configuration1 Register
Offset Address = FC44h
Field 31:15 14 Name PUSRULE Type R R/W Default All 0's 1
Default = 32'h0000_6000
Description Reserved Pause Frame Check Rule When this bit is set, AX88780 accepts pause frame that DA can be any value. 1 = don't check DA field. 0 = check DA is equal to "01 80 C2 00 00 01" Check CRC of received Packet. When this bit is enabled, AX88780 will drop any CRC error packet. 1 = enable 0 = disable Reserved, keep all bits in `0' for normal operation. Duplex Mode.
13
CRCCHK
R/W
1
12:7 6
DUPLEX
R/W R/W
All 0's 0
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ASIX ELECTRONICS CORPORATION
5
RXFLW_EN
R/W
0
4:1 0
-
R/W R/W
4'b0000 0
1 = Full-Duplex mode 0 = Half-Duplex mode RX Flow Control2 To enable RX flow control, driver MUST set this bit & bit8 of RX_CFG. 1 = enable Rx Flow control 0 = disable Reserved, must set to `0s' for normal operation Reserved, must set to `0s' for normal operation
AX88780
4.17 MAC_CFG2--MAC Configuration2 Register
Offset Address = FC48h Default = 32'h0000_0100
Field Name Type Default Description 15:8 R/W 8'h01 Reserved, keep this field in default value for normal operation. 7:2 JamLT R/W 6'h0 Define Jam Limit for backpressure collision account. Normally set this field at 19h. It can avoid HUB port going to partition state due to too many collisions. AX88780 will skip one frame collision backpressure when collision counter equal to JamLT. The collision count will be reset to zero when every transmit frame with no collision or receive a frame with no backpressure collision. 1:0 R/W 2'b00 Reserved, must set to `2'b00' for normal operation
4.18 MAC_CFG3--MAC Configuration3 Register
Offset Address = FC4Ch
Field 15 Name NOABORT Type R/W Default 0
Default = 32'h0000_060E
Description No Abort When this bit is enabled, MAC will keep retry transmit current frame even excessive collision otherwise it will abort current transmission due to excessive collision. 1 = enable 0 = disable Inter-Frame Gap segment1 Inter-Frame Gap segment2
13:7 6:0
IPGR1 IPGR2
R/W R/W
7'h0c 7'h0E
4.19 TXPAUT--TX Pause Time Register
Offset Address= FC54h
Field 31:23 22:0 Name TXPVAL Type R R/W Default
Default = 32'h001F_E000
Description Reserved 23'h1F_E000 TX Pause Time out Driver must set this field to 23'h7F_8000 in initial stage for normal operation. It is used to re-transmit a pause-on frame when pause timer expired and receive buffer still not enough.
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ASIX ELECTRONICS CORPORATION
AX88780
4.20 RXBTHD0--RX buffer Threshold0 Register
Offset Address= FC58h
Field 31:11 10:0 Name RXLOWB Type R R/W Default All 0's 11'h300
Default = 32'h0000_0300
Description Reserved RX Low-Bound Threshold for Pause Operation This field defines the lower-bound threshold of RX buffer for pause operation. If the flow control is enabled, MAC will refer this field for low bound. The unit is a 16-byte. Diver can properly set this field for performance issue. AX88780 is built 32KB buffer for rx operation, so the combination of RXBTHD0 and RXBTHD1 will affect the performance of receive.
4.21 RXBTHD1--RX Buffer Threshold1 Register
Offset Address= FC5Ch
Field 31:11 10:0 Name RXHIGHB Type R R/W Default All 0's 11'h600
Default = 32'h0000_0600
Description Reserved RX Upper-Bound Threshold for Pause Operation This field defines the upper-bound threshold of rx buffer for pause operation. If the flow control is enabled, MAC will refer this field for upper bound. The unit is a 16-byte. Diver can properly set this field for performance issue.
4.22 RXFULTHD--RX Buffer Full Threshold Register
Offset Address= FC60h
Field 31:11 10:0 Name RXFULB Type R R/W Default All 0's 11'h100
Default = 32'h0000_0100
Description Reserved RX Full Threshold This field defines the least capacity of RX buffer. AX88780 will cause RX full if it remains capacity under this value. The unit is 16-byte.
4.23 MISC--Misc. Control Register
Offset Address= FC68h
Field 31:6 5 Name WAKE_LNK Type R R/W
Default = 32'h0000_0003
Default Description All 0's Reserved 0 WAKE-UP by Link-Up Function If this bit is enabled, MAC will drive wakeup pin whenever there is link-up occurrence. The polarity of wakeup pin is according to bit0 of CMD register. 1= enable 0= disable 0 WAKE-UP by Magic Packet If this bit is enabled, MAC will drive wakeup pin whenever there is magic packet detected by hardware. The polarity of wakeup pin is according to bit0 of CMD register. 1= enable wake-up by magic packet
4
WAKE_MAG
R/W
25
ASIX ELECTRONICS CORPORATION
3:2 1
SRST_PHY
R/W R/W
2'b00 1
0
SRST_MAC
R/W
1
0 = disable (default) Reserved Software Reset Internal PHY Driver set this bit to `0' to reset internal PHY. The reset duration is depended on whenever this bit is de-asserted by deriver. 1 = in normal operation 0 = in reset status Software Reset MAC Driver set this bit to `0' to reset MAC. The reset duration is depended on whenever this bit is de-asserted by deriver. 1 = in normal operation 0 = in reset status
AX88780
4.24 MACID0--MAC ID0 Register
Offset Address = FC70h
Field 31:16 15:0 Name MID15_0 Type R R/W Default All 0's 16'h0000
Default = 32'h0000_0000
Description Reserved. MAC ID Address [15:0]. This field defines lower address bit15 to bit0 of MAC. The MACID0, MACID1 and MACID2 combine into 48-bit MAC address. The MAC address format is [47:0] = {MACID2[15:0], MACID1[15:0], MACID0[15:0]}. If the EEPROM is attached, this field will be auto-loaded from EEPROM after hardware reset.
4.25 MACID1--MAC ID1 Register
Offset Address = FC74h
Field 31:16 15:0 Name MID31_16 Type R R/W Default All 0's 16'h0000
Default = 32'h0000_0000
Description Reserved. MAC ID Address [31:16].
4.26 MACID2--MAC ID2 Register
Offset Address = FC78h
Field 31:16 15:0 Name MID47_32 Type R R/W Default All 0's 16'h0000
Default = 32'h0000_0000
Description Reserved. MAC ID Address [47:32].
4.27 TXLEN--TX Length Register
Offset Address = FC7Ch
Field 31:11 10:0 Name MAXTXLEN Type R R/W
Default = 32'h0000_05FC
Default Description All 0's Reserved 11'h5FC Max TX packet size This field defines the maximum raw packet size in transmittance. It is not included 4 bytes FCS.
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ASIX ELECTRONICS CORPORATION
AX88780
4.28 RXFILTER--RX Packet Filter Register
Offset Address = FC80h
Field 31:6 5 4 Name MULTI_HASH Type R R/W R/W
Default = 32'h0000_002C
Default All 0's 1 0 Description Reserved Reserved Receive Multicast packet by lookup hash table. When this is enabled, AX88780 will receive multicast packet by the hash mapping function. It will refer to HASTAB0, HASHTAB1, HASHTAB2 and HASHTAB3 to look up the table. 1 = enable 0 = disable Receive Broadcast packet When this bit is enabled, AX88780 will receive the broadcast packet 1 = enable 0 = disable Receive Directed Packet. If this bit is enabled, AX88780 will compare the destination address field of received packet with the address of MAC (refer to MACID0, MACID1, MACID2). When it is matched and good CRC, the packet will be passed to driver. Otherwise it will be dropped. 1 = enable 0 = disable Receive all Multicast Packets. If this bit is enabled, any multicast packet (good CRC) will be received and passed to driver. 1 = enable 0 = disable Receive Anything. If this bit is enabled, any packet whether it is good or fail will be received and passed to driver. 1 = enable 0 = disable
3
BROADCAST
R/W
1
2
UNICAST
R/W
1
1
MULTICAST
R/W
0
0
RXANY
R/W
0
4.29 MDIOCTRL--MDIO Control Register
Offset Address = FC84h
Field 31:16 15 Name WTEN Type R R/W Default All 0's 0
Default = 32'h0000_0000
Description Reserved Write Enable. Driver enables this bit to issue a write cycle to PHY, it will be cleared when finished the write cycle 1 = enable 0 = disable 0 Read Enable. Driver enables this bit to issue a read cycle to PHY. This bit will be cleared when finished the read cycle 1 = enable 0 = disable 5'b00000 PHY Register Index If driver wants to access PHY, set this field to define the internal register index of PHY.
14
RDEN
R/W
12:8
PHYCRIDX R/W
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ASIX ELECTRONICS CORPORATION
7:5 4:0
PHYID
R R/W
3'b000 Reserved 5'b00000 PHY ID If driver wants to access PHY, set this field to define the address (ID) of PHY. The address of internal PHY is fixed to 10h
AX88780
4.30 MDIODP--MDIO Data Port Register
Offset Address = FC88h
Field 31:16 15:0 Name Type R MDPORT R/W
Default = 32'h0000_0000
Default Description All 0's Reserved All 0's PHY Data Port To or from internal PHY data is put in this field.
4.31 GPIO_CTRL--GPIO Control Register
Offset Address = FC8Ch
Field 31:10 9 Name GPIO1S Type R R/W Default All 0's 0
Default = 32'h0000_0003
Description Reserved GPIO1 Status This bit stands for the pin status of GPIO1 when it is set to input mode. 1 = high state 0 = low state GPIO0 Status This bit stands for the pin status of GPIO0 when it is set to input mode. 1 = high state 0 = low state Reserved GPIO1 Mode Direction This field defines the direction of GPIO1 pin. 1 = input mode 0 = output mode GPIO0 Mode Direction This field defines the direction of GPIO pin. 1 = input mode 0 = output mode
8
GPIO0S
R/W
0
7:2 1
R GPIO1DIR R/W
All 0's 1
0
GPIO0DIR R/W
1
Note: For output mode, software must set the bit0 or bit1 to output mode then set bit8 or bit9.
4.32 RXINDICATOR--Receive Indicator Register
Offset Address= FC90h
Field 31:1 0 Name Type R RXSTART R/W Default All 0's 0
Default = 32'h0000_0000
Description Reserved Receive Start Driver set this bit to start or end receive operation from RX buffer of MAC. 1= Start read RX buffer 0= End read RX buffer
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AX88780
4.33 TXST--TX Status Register
Offset Address = FC94h
Field 31:4 3 2 1 0 Name Type R TXD3FAIL R TXD2FAIL R TXD1FAIL R TXD0FAIL R Default All 0's 0 0 0 0
Default = 32'h0000_0000
Description Reserved TX Descriptor3 Transmit Fail When this bit is set 1, it means MAC fails in transmission of descriptor3. This bit will be self-cleared when driver reads TXST register. TX Descriptor2 Transmit Fail When this bit is set 1, it means MAC fails in transmission of descriptor2. This bit will be self-cleared when driver reads TXST register. TX Descriptor1 Transmit Fail When this bit is set 1, it means MAC fails in transmission of descriptor1. This bit will be self-cleared when driver reads TXST register. TX Descriptor0 Transmit Fail When this bit is set 1, it means MAC fails in transmission of descriptor0. This bit will be self-cleared when driver reads TXST register.
4.34 MDCLKPAT--MDC Clock Pattern Register
Offset Address = FCA0h
Field 31:16 15:8 7:0 Name MDCPAT Type R R/W R/W Default All 0's 8'h80 8'h40
Default = 32'h0000_8040
Description Reserved Reserved, must set to 8'h80 for normal operation MDC Clock Divide Factor This field defines the divide factor of host clock. AX88780 will refer to this field and generate a low speed clock to PHY.
4.35 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter
Offset Address = FCA4h
Field Name Type 31:16 R 15:0 RXCHKERCNT R/W
Default = 32'h0000_0000
Default Description All 0's Reserved All 0's RX Checksum Error Counter If the RXCHKSUM field of RX_CFG register is set to `1', MAC will check the checksum of IP, TCP or UDP packet. Whenever there is checksum error detected, this field will be added one.
4.36 RXCRCNT--RX CRC Error Counter
Offset Address = FCA8h
Field 31:16 15:0 Type R RXCRCCNT R/W Name Default All 0's All 0's
Default = 32'h0000_0000
Description Reserved RX CRC32 Error Counter MAC checks the received packet. If there is a CRC error detect, this field will be added one.
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AX88780
4.37 TXFAILCNT--TX Fail Counter
Offset Address = FCACh
Field 31:16 15:0 Name Type R TXFILCNT R/W Default All 0's All 0's
Default = 32'h0000_0000
Description Reserved TX Fail Counter This field records the number of transmitted error for TX packet.
4.38 PROMDPR--EEPROM Data Port Register
Offset Address = FCB0h
Field 31:16 15:0 Name Type R PROMDP R/W Default All 0's All 0's
Default = 32'h0000_0000
Description Reserved EEPROM Data Port The data to or from EEPROM is set in this field.
4.39 PROMCTRL--EEPROM Control Register
Offset Address= FCB4h
Field Name Type Default 31:15 R All 0's 14:12 ROM_CMD R/W 3'b000
Default = 32'h0000_0000
Description Reserved EEPROM Command Code. Driver set this field to represent what type command will be send to EEPROM device. 3'b110 = read command 3'b111 = erase command 3'b101 = write command Write EEPROM Set to `1' to write EEPROM, it will be cleared when MAC finished the write operation. Read EEPROM Set to `1' to read EEPROM, it will be cleared when MAC finished the read operation. Driver can read PROMDPR register to get the returned data. Reload EEPROM Set to `1' to re-load EEPROM, this bit will be cleared when MAC finished loading operation. Reserved EEPROM Address Set this field to define the address for serial EEPROM access. (only support 16-bit data access, 93C56 type)
11 10 9 8 7:0
ROM_WT ROM_RD ROM_RLD
R/W R/W R/W
0 0 0 0 8'h00
R ROM_ADDR R/W
4.40 MAXRXLEN--Max. RX Packet Length Register
Offset Address= FCB8h
Field 31:11 10:0 Name Type R RXLEN R/W Default All 0's 11'h600
Default = 32'h0000_0600
Description Reserved Max RX Packet length This field defines the max length of received packet. It doesn't include 4-byte CRC.
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AX88780
4.41 HASHTAB0--Hash Table0 Register
Offset Address = FCC0h
Field 31:16 15:0 Name Type R HTAB0 R/W Default All 0's 16'h0000
Default = 32'h0000_0000
Description Reserved Hash table: bit15~bit0 Driver sets HASHTAB0, HASHTAB1, HASHTAB2 and HASHTAB3 to define 64-bit hash table. AX88780 will refer this table to check multicast packet if multicast filter is enabled for RX. When AX88780 receives a packet then it extracts the destination address (DA). The DA is calculated by CRC32 algorithm. After the operation, AX88780 will grab the MSB[31:27] of result as hash table index. The range of index is from 0 to 63
4.42 HASHTAB1--Hash Table1 Register
Offset Address = FCC4h
Field 31:16 15:0 Name Type R HTAB1 R/W Default All 0's 16'h0000
Default = 32'h0000_0000
Description Reserved Hash table: bit31~bit16
4.43 HASHTAB2--Hash Table2 Register
Offset Address = FCC8h
Field 31:16 15:0 Name Type R HTAB2 R/W Default All 0's 16'h0000
Default = 32'h0000_0000
Description Reserved Hash table: bit47~bit32
4.44 HASHTAB3--Hash Table3 Register
Offset Address = FCCCh
Field 31:16 15:0 Name Type R HTAB3 R/W Default All 0's 16'h0000
Default = 32'h0000_0000
Description Reserved Hash table: bit63 ~ bit48
4.45 DOGTHD0--Watch Dog Timer Threshold0 Register
Offset Address = FCE0h
Field 31:16 15:0 Name Type R DOGTH0 R/W
Default = 32'h0000_FFFF
Default Description All 0's Reserved 16'hFFFF Watch Dog Timer Low Word This register and DOGTHD1[7:0] are defined to an expired threshold in
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ASIX ELECTRONICS CORPORATION
internal watch dog counter. The threshold {[DOGTHD1, DOGTHD0] is a 24-bit value. To multiply 24-bit value with cycle period of a host clock is the duration.
AX88780
4.46 DOGTHD1--Watch Dog timer Threshold1 Register
Address = FCE4h
Field 31:8 7:0 Name Type R DOGTH1 R/W
Default = 32'h0000_0000
Default Description All 0's Reserved 8'h0 Dog Timer High Byte. This filed and DOGTHD0[15:0] combine to a 24-bit field.
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AX88780
5.0 PHY Register
AX88780 is built a high performance 10/100M PHY for cost-effective. Driver can access these registers of PHY by in-directed mechanism. For write operation, software firstly sets data to MDIODP register, then sets index and write enable bit to MDIOCTRL register. AX88780 will access PHY by internal interface and clear the write enable bit whenever the operation finished. For read operation, driver sets the index and read enable bit to MDIOCTRL register, then polls the read-enable bit. The returned data will be put in MDIODP register whenever the read-enable bit is cleared. Index 00h 01h 02h 03h 04h 05h 06h Name BMCR BMSR PHYIDR0 PHYIDR1 ANAR ANLPAR ANER Table 9 : PHY Register Mapping Description Basic Mode Control Register Basic Mode Status Register PHY Identifier 0 Register PHY Identifier 1 Register Auto-negotiation Advertisement Register Auto-negotiation Link Partner Ability Register Auto-negotiation Expansion Register
The following abbreviations apply to below sections for detained register description. Access type R = read only RW= read/write Attribute: LL = latch low LH = latch high SC = Self-clearing PS = Value is permanently set X = don't care
5.1 BMCR--Basic Mode Control Register
Index = 00h
Field 15 14 13 12 Name PHYRST LOOPBACK SPDSEL Type R/W R/W R/W Default 0, SC 0 1 1 Description Soft reset: 1 = software reset PHY, this bit will be cleared when reset finish. 0 = normal operation Loop back operation: 1 = Loop back enable 0 = Loop back disable Speed selection: 1 = 100Mb/s 0 = 10Mb/s Auto-negotiation enable: 1 = enable, bit8 and bit13 will be ignored when this bit is enabled. 0 = disable, bit8 and bit13 of this register determine the link speed and mode. Power down: 1 = power-down enable 0 = normal operation Reserved Auto-negotiation restart: 1=Restart auto-negotiation, this bit will be cleared when finish
AUTONEG_EN RW
11 10 9
PHYPWDN
R/W
0 0 0
R AUTONEG_RS R/W
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8 7 6:0
DPLX COLTST -
R/W R/W R
1 0 X
negotiation. 0=normal operation Duplex mode: 1=Full-duplex operation 0= Normal operation Collision test: 1=Enable collision test 0= Normal operation Reserved
AX88780
5.2 BMSR--Basic Mode Status Register
Index = 01h
Field 15 14 13 12 11 10:7 6 5 4 3 2 1 0 Name 100BCAP 100BFUL 100BHAF 10BFUL 10BHAF MFPS Type R R R R R R R Default Description 0, PS 100Base-T4 capability 0 = AX88780 is not able to execute 100 BASE-T4 mode. 1, PS 100BASE-TX full-duplex capability: 1= AX88780 is able to perform in 100BASE-TX full-duplex mode. 1, PS 100BASE-TX half-duplex capability: 1 = AX88780 is able to perform in 100BASE-TX half-duplex mode. 1, PS 10BASE-T full-duplex capability: 1 = AX88780 is able to perform in 10BASE-T full-duplex mode. 1, PS 10BASE-T half-duplex capability: 1 = AX88780 is able to perform in 10BASE-T half-duplex mode. All 0's Reserved, default 4'b0000 0, PS Management frame preamble suppression: 0 = AX88780 will not accept management frames with preamble suppressed. 0 Auto negotiation completion: 1 = auto-negotiation process is complete. 0 = auto-negotiation process is not completed 0, LH Remote fault status: 1 = The link partner signals a far-end fault, read to clear. 0 = Remote fault condition is not detected 1, PS Auto configuration ability: 1 = AX88780 is able to perform auto-negotiation 0, LL Link status: 1= Valid link is established, (100Mb/s or 10Mb/s operation) 0= Valid link is not established 0, LH Jabber detection: 1= Jabber condition is detected. 0 = Jabber condition is not detected 1, PS Extended capability: 1= Extended register capable 0= Basic register capability only.
AUTONEST R RFST RC
AUTOCFG R LNKST JABDET EXTCAP R R R
5.3 PHYIDR0--PHY Identifier 0 Register
Index = 02h
Field 15:0 Name Type OUIMSB R Default 16'h003B PS Description OUI most significant bits. Bits 3 to 18 of the OUI are mapped to bits 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored
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AX88780
5.4 PHYIDR1--PHY Identifier 1 Register
Index = 03h
Field 15:10 9:4 3:0 Name Type OUILSB R MANMODE R RECNUM R Default Description 6'b000110 OUI lease significant bits. 6'b000011 Manufacture's mode number 4'b0001 Revision number Default 16'h1831 PS
5.5 ANAR--Auto-negotiation Advertisement Register
Index = 04h
Field 15 14 13 12:11 10 PF 9 8 7 6 5 4:0 Name NXTP Type R R R R R/W R Default 0, PS 0 0 X 0 0, PS 1 1 1 1 5'b00001 Description Next page indication: Not support Reserved Remote fault: Not support fault condition detected. Reserved Pause function: AX88780 does not support this function in PHY layer. The pause function will support with MAC operation. 100BASE-T4 support: Not support 100BASE-TX full-duplex support: 1=enable 100BASE-TX full duplex 0=disable 100BASE-TX full-duplex 100BASE-TX half-duplex support: 1=enable 100BASE-TX half-duplex 0=disable 100BASE-TX half-duplex. 10BASE-T full-duplex support: 1=enable 10BASE-T full-duplex 0=disable 10BASE-T full duplex. 10BASE-T half-duplex support: 1=enable 10BASE-T half-duplex 0=disable 10BASE-T half-duplex. Protocol selection bits: AX88780 support IEEE 802.3u CSMA/CD.
100BSUP
100BFULSUP R/W 100BHAFSUP R/W 10BFULSUP R/W 10BHAFSUP R/W PROSEL R/W
5.6 ANLPAR--Auto-negotiation Link Partner Ability Register
Index = 05h
Field 15 14 13 Name PNRNXT PNRACK PNRRF Type R R R Default Description 0 Next page indication: 1= Link partner is next page enabled. 0= Link partner is not next page enabled 0 Acknowledgement: 1= Link partner ability for reception of data word is acknowledged 0= Link partner ability for reception of data word is not acknowledged. 0 Remote fault: (from link partner view)
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12:11 10 PNRPAUS 9 8 7 6 5 4:0 PNR100B
R R R
PNR100BFUL R PNR100BHAF R PNR10BFUL R PNR10BHAF R PNRPROSEL R
1= Remote fault is indicated by link partner. 0= Remote fault is not indicated by link partner. 2'b00 Reserved 0 Pause: 1= Pause operation is supported by link partner. 0= Pause operation is not support by link partner. 0 100Base-T4 support: 1 = 100Base-T4 is supported by link partner. 0 = 100Base-T4 is not supported by link partner. 0 100BASE-TX full-duplex support: 1 = 100BASE-T full-duplex is supported by link partner. 0 = 100BASE-TX full-duplex is not supported by link partner. 0 100BASE-TX half-duplex support: 1 = 100BASE-TX half-duplex is supported by link partner. 0 = 100BASE-TX half-duplex is not supported by link partner. 0 10BASE-T full-duplex support: 1 = 10BASE-T full-duplex is supported by link partner. 0 = 10BASE-T full-duplex is not supported by link partner. 0 10BASE-T half-duplex support: 1 = 10BASE-T half-duplex is supported by link partner. 0 = 10BASE-T half-duplex is not supported by link partner. 5'b00000 Protocol selection bits: Link partner's binary encoded protocol selector.
AX88780
5.7 ANER--Auto-negotiation Expansion Register
Index = 06h
Field 15:5 4 3 2 1 0 Name PARDETF Type R R Default All 0's 0, LH 0 0, PS 0, LH 0 Description Reserved, Parallel detection fault: 1 = Fault is detected via parallel detection function 0 = Fault is not detected Link partner next page enable: 1 = Link partner is next page enabled 0 = Link partner is not next page enabled. PHY next page enable: 1 = PHY is next page enabled 0 = PHY is not next page enabled. New page reception: 1 = New page is received 0 = New page is not received. Link partner auto-negotiation enable: 1 = Auto-negotiation is supported by link partner, 0 = Auto-negotiation is not supported by link partner.
LNKPNRNXT R PHYNXTPG R NPREC R
LNKPNRAN R
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AX88780
6.0 Electrical Specification and Timings 6.1 DC Characteristics
6.1.1 Absolute Maximum Ratings Symbol Description Min Max Units TSTG Storage Temperature -40 +150 C VCC3 Power supply of 3.3V IO -0.3 VCC33 + 0.3 V VCC3R Power supply of 3.3V IO for regulator -0.3 VCC3R + 0.3 V VCC2 Power supply of 2.5V IO -0.3 VCC25 + 0.3 V VCC2A Power supply of 2.5V for analog core -0.3 VCC2A + 0.3 V VI3 Input 3.3Vvoltage with 5V tolerance -0.3 +5.5 V VI2 Input 2.5V voltage with 3.3V tolerance -0.3 +3.9 V Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability. 6.1.2 General Operation Conditions Symbol Tj VCC2 VCC3 VCC3R VCC2A VI3 VI2 Description Junction temperature Supply Voltage of 2.5V Supply Voltage of 3.3V Supply voltage of 3.3V for regulator Supply voltage of 2.5V for analogy core Input voltage of 3.3V with 5V tolerance Input voltage of 2.5V with 3.3V tolerance Min 0 2.25 3.0 3.0 2.25 0 0 Typ 2.5 3.3 3.3 2.5 3.3 2.5 Max 115 2.75 3.6 3.6 2.75 5.25 3.6 Units C V V V V V V
6.1.3 Leakage Current and Capacitance Symbol IIN IOZ COUT CBID Description Input Leakage Current Tri-state leakage current Output capacitance Bi-directional buffer capacitance Min -10 -10 Typ 1 1 3.1 3.1 Max +10 +10 Units A A pF pF
6.1.4 DC Characteristics of 2.5V IO Pins Symbol VCC2 Vil Vih Vol Voh Rpu Rpd Description Power supply of 2.5V IO Input low voltage Input high voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Min 2.25 1.7 2.4 Typ 2.5 75 75 Max 2.75 0.7 0.4 Units V V V V V K K
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6.1.5 DC Characteristics of 3.3V IO Pins Symbol VCC3 Vil Vih Vol Voh Rpu Rpd Description Power supply of 3.3V IO Input low voltage Input high voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Min 3.0 2.0 2.4 Typ 3.3 75 75
AX88780
Max 3.6 0.78 0.4 Units V V V V V K K
6.1.6 Transmission Characteristics Symbol Vpp 2xVtxa Tr/Tf Tjit Vtxov Description Peak-to-Peak differential output voltage Peak-to-Peak differential output voltage, Signal rising/falling time Output jitter Overshoot Conditions 10BASE-T mode 2xVtxa 100BASE-TX 100BASE-TX 100BASE-TX 100BASE-TX Min. 4.5 1.9 3 Typ. 5 2 4 Max. Units 5.5 V 2.1 V 5 ns 1.4 ns 5 %
6.1.7 Reception Characteristics Symbol Rimp Vsqu Vcom Lfree Description Reception impedance Differential squelch voltage Common mode input voltage Max error-free cable length Conditions 10BASE-TX Min. 5 300 1.2 100 Typ. 400 1.6 Max. 500 2 Units K mV V Meter
+Vtxa +Vtxon 90%
10% 0V
Tr
Figure 6 : Transmit waveform specification
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6.1.8 Power Consumption Description Current consumption of VCC2, 2.5V Power On with auto-negotiation Current consumption of VCC2, 2.5V 10M with traffic Current consumption of VCC2, 2.5V 100M with traffic IVCC3 Current consumption of VCC3, 3.3V Power On with auto-negotiation Current consumption of VCC3, 3.3V 10M with traffic Current consumption of VCC3, 3.3V 100M with traffic Note Based on 125M HCLK reference clock 6.1.9 Thermal Characteristics A. Testing Condition Environment PCB Layer (2S2P) Maximum junction temperature (oC) -- TJ Ambient temperature (oC) -- TA Input Power (W) -- P B. Junction to ambient thermal resistance Symbol Min 1 JA (0 m/s airflow) Typ 46.3 40.3 38.6 37.5 Max 4 125 65 1 Symbol IVCC2 Min Typ 220 200 157 2.5 2.5 2.7
AX88780
Max Units mA mA mA mA mA mA
Units o C/W
o o o
JA JA JA
(1 m/s airflow) (2 m/s airflow) (3 m/s airflow)
-
C/W C/W C/W
1: Note
JA
=
defined as below
JA JA
TJ - T A P
: thermal resistance
TJ : junction temperature TA: ambient temperature P : input power (watts) TJ = TA + (P X JA ) C. Power Dissipation Air Flow (m/s) Power Dissipation (watt)
0 1.29
1 1.48
2 1.55
3 1.6
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AX88780
6.2 A.C. Timing Characteristics
6.2.1 Host Clock A. Host site reference clock Description Reference frequency Reference clock duty cycle B. PHY site reference clock Description Reference frequency Reference clock duty cycle 6.2.2 Reset Timing Min 40 Min 25 - 0005% 40 Typ. 100 50 Typ. 25 50 Max 60 Max 25 + 0.005% 60 Units MHz % Units MHz %
HCLK R ST_N
T rst
Symbol Trst Reset pulse width
Description
Min 2
Typ. -
Max -
Units ms
6.2.3 Host Single Write
HCLK
Timing
Tsetup
CSN
WEN
Tvalid_cycle
HA[15:1]
Valid address
Tar
HD[31:0]
Valid data
Tad
Symbol Description Tsetup CSN,WEN to HCLK setup timing Tar HA exceed to WEN timing Tad HA exceed to WEN timing Tvalid_cycle A Valid write cycle timing
Min 6 0 0 3
Typ. -
Max -
-
-
Units ns HCLK HCLK HCLK
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AX88780
6.2.4 Host Fast Write Timing
HCLK CSN
HA[15:1]
Address
Address + 4
Address + 8
HD[31:0]
WEN
Valid data
Valid data
Valid data
Twen
Tidle
Symbol Twen Tidle
Description Valid write cycle timing WEN de-asserted timing
Min 3 1
Typ. -
Max -
Units HCLK HCLK
6.2.5 Host Single Read Timing
Tsetup
HCLK
CSN
OEN
HA[15:1]
Tar
Valid address
Tvalid_data
HD[31:0]
Valid data
Symbol Tsetup Tar Tad Tvalid_data
Description CSN,OEN to HCLK setup timing HA exceed to OEN timing HA exceed to OEN timing Available data to OEN timing
Min 4 0 0 3
Typ. -
Max -
-
-
Units ns HCLK HCLK HCLK
6.2.6 Host Fast Read Timing
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AX88780
HCLK CSN
Address OEN
Address + 4
Address + 8
Toe
HD[31:0]
Tidle
Valid data Valid data Valid data
Invalid data
Symbol Description Tvalid_data Available data to OEN timing Tidle OEN de-asserted timing
Min 3 1
Typ. -
Max -
Units HCLK HCLK
6.2.7 MII Receive Timing (100Mb/s)
RXD[3:0] RXDV
RXCLK Thold
Tsetup
Trxclk
Symbol Trxclk Tsetup Thold
Description RXCLK clock cycle time* RXD[3:0] RXDV setup time for RXCLK RXD[3:0], RXDV hold timing for RXCLK
Min 5 3
Typ. 40 -
Max -
Units ns ns ns
6.2.8 MII Transmit Timing (100Mbps)
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ASIX ELECTRONICS CORPORATION
AX88780
Ttxclk
TXCLK
Thold
Tsetup
TXD[3:0] TXEN
Tdelay
Symbol Description Min Ttxclk TXCLK reference clock* Tdelay TXD[3:0], TXEN delay timing for TXCLK Tsetup TXD[3:0], TXEN setup time 28 Thold TXD[3:0], TXEN hold time 5 *Note: for 10Mbps, the typical value of Ttxclk shall scale to 400ns 6.2.9 MDIO Timing
Tclk
Typ. 40 -
Max 10
Units ns ns ns ns
MDC
MDIO (output)
Tod
MDIO (input)
Ts Th
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ASIX ELECTRONICS CORPORATION
AX88780
Symbol Description Tclk MDC clock timing* Tod MDC falling edge to MDIO output delay Ts MDIO data input setup timing Th MDIO data input hold timing *Note: hclk is 66MHz case. 6.2.10 Serial EEPROM Timing Min Typ. 2144 Max 32 Units ns ns ns ns
10 4
T c lk
EECLK
EEDI (o u tp u t)
Tod
EEDO (in p u t)
Ts
T scs
Th
T hcs
T lc s
EECS
Symbol Description Tclk EECLK clock timing* Tod EECLK falling edge to EEDI output delay Ts EEDO data input setup timing Th EEDO data input hold timing Tscs EECS output valid to EECLK rising edge Thcs EECLK falling edge to EECS invalid timing Tlcs Minimum EECS low timing *Note: hclk is 66MHz case.
Min
10 16 1040 0 -
Typ. 2192 -
Max 5 -
1040
-
Units ns ns ns ns ns ns ns
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ASIX ELECTRONICS CORPORATION
AX88780
7.0 Package Information
He E
A A2
A1
Hd
D
pin 1
b
e
SYMBOL MIN.
A1 A2 A b D E e Hd He L L1 0 15.85 15.85 0.45 0.13 13.90 13.90 0.05 1.35
MILIMETER NOM
0.1 1.4 1.45 1.6 0.18 14.00 14.00 0.40 16.00 16.00 0.60 1.00 7 16.15 16.15 0.75 0.23 14.10 14.10
MAX
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ASIX ELECTRONICS CORPORATION
L
L1
AX88780
Ordering Information AX88780 Product name L Package LQFP F F: Lead Free
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AX88780
Appendix
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ASIX ELECTRONICS CORPORATION
AX88780
Revision History
Revision V1.0 Date Oct/4/2005 Comment 1. First edition
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AX88780
4F, NO.8, HSIN ANN RD., HSINCHU SCIENCE PARK, HSINCHU, TAIWAN, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 Email: support@asix.com.tw Web: http://www.asix.com.tw
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